The development of semiconductor switching technology for high power applications in motor drive circuits, appliance controls and lighting ballasts, for example, began with the bipolar junction transistor. As the technology matured, bipolar devices became capable of handling large current densities in the range of 40-50 A/cm.sup.2, with blocking voltages of 600 V.
Despite the attractive power ratings achieved by bipolar transistors, there exist several fundamental drawbacks to the suitability of bipolar transistors for all high power applications. First of all, bipolar transistors are current controlled devices. For example, a large control current into the base, typically one fifth to one tenth of the collector current, is required to maintain the device in an operating mode. Even larger base currents, however, are required for high speed forced turn-off. These characteristics make the base drive circuitry complex and expensive. The bipolar transistor is also vulnerable to breakdown if a high current and high voltage are simultaneously applied to the device, as commonly required in inductive power circuit applications, for example. Furthermore, it is difficult to parallel connect these devices since current diversion to a single device occurs at high temperatures, making emitter ballasting schemes necessary.
The power MOSFET was developed to address this base drive problem. In a power MOSFET, a gate electrode bias is applied for turn-on and turn-off control. Turn-on occurs when a conductive channel is formed between the MOSFET's source and drain regions under appropriate bias. The gate electrode is separated from the device's active area by an intervening insulator, typically silicon dioxide. Because the gate is insulated from the active area, little if any gate current is required in either the on-state or off-state. The gate current is also kept small during switching because the gate forms a capacitor with the device's active area. Thus, only charging and discharging current ("displacement current") is required. The high input impedance of the gate, caused by the insulator, is a primary feature of the power MOSFET. Moreover, because of the minimal current demands on the gate, the gate drive circuitry and devices can be easily implemented on a single chip. As compared to bipolar technology, the simple gate control provides for a large reduction in cost and a significant improvement in reliability.
These benefits are offset, however, by the high on-resistance of the MOSFET's active region, which arises from the absence of minority carrier injection. As a result, the device's operating forward current density is limited to relatively low values, typically in the range of 10 A/cm.sup.2, for a 600 V device, as compared to 40-50 A/cm.sup.2 for the bipolar transistor.
On the basis of these features of power bipolar transistors and MOSFET devices, hybrid devices embodying a combination of bipolar current conduction with MOS-controlled current flow were developed and found to provide significant advantages over single technologies such as bipolar or MOSFET alone. Thus, in the insulated gate transistor (IGT), disclosed in an article by inventor B. J. Baliga, and M. S. Adler, R. P. Love, P. V. Gray and N. Zommer, entitled "The Insulated Gate Transistor: A New Three terminal MOS Controlled Bipolar Power Device," IEEE Trans. Electron Devices, ED-31, pp. 821-828 (1984), on-state losses were shown to be greatly reduced when compared to power MOSFETs. This was caused by the conductivity modulation of the IGT's drift region during the on-state. Moreover, very high conduction current densities in the range of 200-300 A/cm.sup.2 can also be achieved. Accordingly, an IGT can be expected to have a conduction current density approximately 20 times that of a power MOSFET and five (5) times that of an equivalently sized bipolar transistor. Typical turn-off times for the IGT can be expected to be in the range of 10-50 .mu.s. A cross-sectional representation of a typical insulated gate transistor is shown in FIG. 1.
Although gate-controlled transistors, such as the IGT, represent an improvement over using bipolar or MOSFET devices alone, even lower conduction losses can be expected by using a thyristor. This is because thyristors offer a higher degree of conductivity modulation and a lower forward voltage drop when turned on. Consequently, the investigation of thyristors is of great interest so long as adequate methods for providing forced gate turn-off can also be developed. As will be understood by one skilled in the art, a thyristor in its simplest form comprises a four-layer P1-N1-P2-N2 device with three P-N junctions in series: J1, J2, and J3, respectively. The four layers correspond to the anode (P1), the first base region (N1), the second base or P-base region (P2) and the cathode (N2), respectively. In the forward blocking state, the anode is biased positive with respect to the cathode and junctions J1 and J3 are forward biased and J2 is reversed-biased and most of the forward voltage drop occurs across the central junction J2. In the forward conducting state, all three junctions are forward biased and the voltage drop across the device is very low and approximately equal to the voltage drop across a single forward biased P-N junction.
An inherent limitation to the use of thyristors for high current applications is sustained latch-up, however, arising from the coupled P1-N1-P2 and N1-P2-N2 bipolar transistors which make up the four layers of the thyristor. This is because sustained thyristor latch-up can result in catastrophic device failure if the latched-up current is not otherwise sufficiently controlled by external circuitry or by reversing the anode potential. Sustained latch-up can occur, for example, when the summation of the current gains for the thyristor's regeneratively coupled P1-N1-P2 and wide base P1-N2-P2 transistors exceeds unity. An alternative to providing external circuitry or reversing the anode potential to obtain turn-off, however, is to use a MOS-gate for controlling turn-on and turn-off.
Several methods for obtaining MOS-gate control over thyristor action, including latch-up, exist. For example, in the MOS-controlled thyristor (MCT), turn-off is provided by shorting the emitter-base junction of the N-P-N transistor to thereby produce a reduction in gain. This form of control ideally raises the holding current of the thyristor to a level above the operating current level. Accordingly, an MCT structure has been reported which utilizes a P-channel MOSFET integrated into the cathode region of a thyristor for turn-off control, and an N-channel MOSFET integrated into the P-base region for turn-on control, as shown in FIG. 2. This device and its complementary counterpart are described in an article by V. A. K. Temple, entitled "The MOS Controlled Thyristor," published in IEDM Technology Digest, Abstract 10.7, pp. 282-285, (1984). However, the maximum controllable current density, which is a direct measure of a device's ability to turn-off, is limited by the MOSFET inversion-layer channel resistance and other resistances in the base region. Because of the lower mobility for holes in silicon, MCT's built from n-type high-voltage drift layers exhibit poor current turn-off characteristics.
Other examples of MOS-gated thyristors include the depletion-mode thyristor (DMT), shown in FIG. 3, which overcame many of the drawbacks associated with the MCT. In the DMT, a depletion-mode MOSFET is placed in series with the base of the P-N-P transistor. Accordingly, once the thyristor is turned-on, current flow can be shut off by application of a negative gate bias. This eliminates the base drive by pinching off the base current to the P-N-P transistor and shuts off the device.
Recently, a base resistance controlled thyristor (BRT) was described in U.S. Pat. No. 5,099,300, to inventor B. J. Baliga, and an article entitled "A New MOS-Gated Power Thyristor Structure with Turn-Off Achieved by Controlling the Base Resistance," by M. Nandakumar, inventor B. J. Baliga, M. Shekar, and S. Tandon and A. Reisman, IEEE Electron Device Letters, Vol. 12, No. 5, pp. 227-229, May, 1991, both of which are hereby incorporated herein by reference. The BRT operates by modulating the lateral P-base resistance of the thyristor using MOS gate control. Operational BRTs with 600-volt forward blocking capability, such as the one shown in FIG. 4, have been developed. FIG. 4 is a reproduction of FIG. 1 from the aforesaid Nandakumar, et al. article. The BRT can be turned-off by application of a negative bias to a P-channel enhancement-mode MOSFET to thereby reduce the resistance of the P-base by shunting majority charge carriers to the cathode. As will be understood by one skilled in the art, the reduction in P-base resistance results in an increase in the device's holding current to above the operational current level and shuts-off the device.
In another device, described in an article entitled "The MOS-Gated Emitter Switched Thyristor," by inventor B. J. Baliga, published in IEEE Electron Device Letters, Vol. 11, No. 2, pp. 75-77, February, 1990, turn-on is achieved by forcing the thyristor current to flow through an N-channel enhancement-mode MOSFET and floating N.sup.+ emitter integrated within the P-base region. This article is hereby incorporated herein by reference. A cross-sectional representation of this structure and equivalent circuit is shown in FIGS. 5A and 5B, which are reproductions of FIG. 1 from the aforesaid Baliga article. As will be understood by one skilled in the art, the length of the floating N.sup.+ emitter region, which determines the value of large resistance R shown in FIG. 5B, controls the holding and triggering current for the device. Turn-off of the emitter switched device (EST) is accomplished by reducing the gate voltage on the MOSFET to below the threshold voltage. This cuts off the floating N.sup.+ region from the cathode and ideally shuts-off the device.
Unfortunately, the integration of the MOSFET into the P-base region causes a parasitic thyristor to be formed, as shown in FIG. 5A, wherein the N.sup.+ source region of the N-channel MOSFET also comprises the N.sup.+ emitter of the vertical parasitic thyristor between the anode and cathode. If this thyristor turns-on, the EST can no longer be turned off by reducing the MOSFET gate voltage to zero. Turn-on of the parasitic thyristor is initiated by the onset of electron injection from the N.sup.+ emitter region of the parasitic thyristor when forward biased, and is dictated by the resistance of the P-base under the N.sup.+ emitter region. The likelihood that parasitic latch-up will occur can be reduced if the P-base resistance (small R) is lowered by making the length of the N.sup.+ emitter region small and by using a P.sup.+ diffusion to reduce the sheet resistance of the P-base. By keeping the resistance under the N.sup.+ emitter of the parasitic thyristor as small as possible, the likelihood that the P.sup.+ /N.sup.+ junction will become forward biased when the thyristor is turned-on is reduced. The likelihood of injection of electrons from the N.sup.+ emitter can also be reduced by shorting the P.sup.+ diffusion to the cathode, as shown. Notwithstanding these techniques to prevent latch-up, however, a multicell EST switching device rated for 1 amp has been shown to be susceptible to parasitic latch-up failure at about 2.5 amps for a gate voltage of 10 volts for a 600 volt device. This low latch-up level limits the suitability of using emitter switched devices for higher current applications.
Other attempts to limit the likelihood of sustained parasitic latch-up have been made. For example, in a related copending application entitled Emitter Switched Thyristor with Base Resistance Control, Ser. No. 07/897,456, filed Jun. 10, 1992, by M. S. Shekar, M. Nandakumar and inventor B. J. Baliga, the probability of sustained parasitic thyristor action preventing turn-off was reduced by incorporating a current diverting means adjacent the parasitic thyristor to thereby reduce the effective resistance of the second base region during turn-off and further inhibit latch-up by preventing the forward biasing of the P.sup.+ /N.sup.+ junction beneath the cathode.
Notwithstanding these attempts to limit the susceptibility to sustained parasitic thyristor latch-up, the presence of an adjacent parasitic thyristor between the anode and cathode poses a risk that under certain operating conditions, parasitic latch-up will occur.